The present invention relates generally to an arithmetic logic unit (ALU) and, more specifically, to an improved arithmetic logic unit having reduced propagation delay.
An arithmetic logic unit, as illustrated in FIG. 1, generally includes an AND matrix 20 which receives two signals to be added A.sub.n and B.sub.n in its true and complemented form. The output of the AND matrix are the four combinations of the four input signals, namely, AB, A -B, -AB and -A-B. These AND terms are provided to a propagation OR gate matrix 22 and a generation OR gate matrix 24. The propagation OR gate matrix 22 receives all four of the signals wherein the generation OR gate matrix 24 receives only the first three of the AND signals. The propagation OR gate matrix 22 also is controlled by control signals K0 through K3 and the generation OR gate matrix 24 is controlled by the control signals L0 through L2. The control signals K0 through K3 and L0 through L2 select the appropriate combination from the AND matrix to produce the propagate signal P.sub.n and the generate signal G.sub.n to perform arithmetic functions, namely, addition of A plus B, substraction A minus B, subtraction B minus A and A logical B. The propagate term P.sub.n is also known as the sum term and the generate term G.sub.n is also known as the product term. These signals are provided to carry and sum logic 26 which combines the propagation and generate signals with the carry-in signal C.sub.n-1. It produces a sum signal S.sub.n and an output carry signal C.sub.n. It should be noted that FIG. 1 is for a single digit and a plurality of them are used depending upon the size of the adder.
A typical example of arithmetic logic adder as illustrated in FIG. 1 is described in U.S. Pat. No. 4,263,660 to Priosde. The function select provides control signals to the propagate and generate OR gates whose output is provided to the logic transfer and carry look ahead circuits. This is a typical parallel adder with series carry propagate. The major problem of parallel adders is the delay produced by the series propagation of the carry signal. U.S. Pat. Nos. 4,052,604 and 4,054,788 to Maitland et al reduces the carry propagation time by calculating the carry of the least significant digits independent of the corresponding sum bits to allow propagation of the carry bits to the more significant bit before completion of the summation of the least significant digits. To increase the speed of the carry propagation, carry look ahead circuits have been provided.
Another method of reducing the number of elements used to perform the carry and sum signals as well as to decrease the propagation time of the carry is illustrated in U.S Pat. No. 3,843,876 to Fette et al wherein some common elements are used to simultaneously calculate the sum and the carry and precharges the carry line which is later discharged since a majority of the carry signals require charge lines. Another example of this type of circuit is illustrated in U.S. Pat. No. 4,152,775 to Schwartz.
The adder structure of FIG. 1 is the heart of an arithmetic logic unit and may be used to perform the multitude of functions including addition, subtraction and any logical combination of the two input variables A.sub.n and B.sub.n. The ALU also includes a shifter/swapper at the output of the adder for shifting right and left as well as bit swapping. Prior art ALUs used input registers for the two words to be added A and B and an output register for the sum S.sub.n. A prior art cycle generally includes for a binary coded decimal (BCD) in excess 3 code, adding the A register plus the constant 6 and storing the sum back in the A register in the first cycle, a second cycle of adding the A and B register and storing the sum and for the third cycle adding the sum plus a constant to derive the compensated binary coded decimal. The three cycles are independent and require three passes through the ALU and this requires an excessive amount of time. It should also be noted that prior ALUs use latches as well as registers for the storing of the sums and carries as well as for the propagate and generate signals. These latches and registers require control pulses which must be produced by additional circuitry and add delays.